日本ゼオライト学会　刊行物 Publication of Japan Zeolite Association

A “pore engineering”, which is a method for controlling the memory performance of conducting-bridge random access memory (CB-RAM) by regarding the polycrystalline oxide memory layer as a nano-porous body, is proposed. This method enables controlling important memory parameters by providing appropriate solvents to the pores, and by controlling the pore size and physical and chemical properties of the pore surface. In this paper, a forming and set voltages, and their dispersions were confirmed to be reduced by supplying solvents with high solubility of Cu to the HfO₂ layer of Cu/HfO₂/Pt structures. Not only the reduction of switching voltages and their dispersion but also the improvement of both immunity against external disturbance and cycling endurance were achieved by supplying ionic liquid. On the basis of this concept of “pore engineering”, very low power consumption and ultra high density can be achieved by using an ionic liquid as the solvent and a metal organic framework (MOF) as the memory layer of CB-RAM.